1. Field of the Invention
The invention relates to a failure analysis equipment to be used for an electronic circuit and a method of making a failure analysis in an electronic circuit, and more particularly to such an equipment and method to be used for an electronic circuit arranged on a substrate such as a printed wiring board.
2. Description of the Related Art
If an integrated circuit or an electronic circuit comprising discrete elements such as active elements and passive elements both formed on a substrate such as a printed wiring board does not operate in a desired manner, a failure analysis equipment is often used for clearing up the cause thereof and/or identifying a failure site of an electronic circuit.
FIG. 1 illustrates a conventional failure analysis system to be used for identifying a failure site of an electronic circuit. The illustrated failure analysis equipment comprises a constant voltage supply 20 for supplying a constant voltage to an electronic circuit 100 to be failure-analyzed, a test signal emitter 21 for emitting test signals to the target electronic circuit 100, and an in-circuit tester 22 for comparing measured voltages of various sections of the target electronic circuit 100 with a predetermined value to thereby determine voltage and/or current in those sections of the target electronic circuit 100 are normal or abnormal.
In this failure analysis equipment, a constant voltage is applied to the target electronic circuit 100, and then voltages of various sections of the target electronic circuit 100 are measured. Then, the in-circuit tester 22 compares the thus measured voltages with a design value or calculates a current from those voltages to thereby determine whether an abnormal current is running through the target electronic circuit 100 or not. In addition, the in-circuit tester 22 observes response from the target electronic circuit 100 when the test signal emitter 21 emits test signals to the target electronic circuit 100. Thus, failure sites in the target electronic circuit 100 are identified, and the causes of failures are investigated.
FIG. 2 illustrates another example of a conventional failure analysis equipment. The illustrated failure analysis equipment is to be used only for an analog integrated circuit. A pair of probes 23 are made in physical contact with an integrated circuit chip 24 mounted on an analog integrated circuit device 100 to be failure-analyzed. The probes 23 are in electrical communication with a detector 25, and thus the detector 25 can measure a voltage of a point of the chip 24 with which the probes 23 are in contact. A device driving system 26 supplies voltage, current and/or signals to and thereby operates the target circuit device 100 for testing.
In operation, the device driving system 26 is driven to test the performance of the integrated circuit device 100. Then, the detector 25 measures a voltage of a point of the chip 24 with which the probes 23 are in contact. Based on the thus measured voltage, it is possible to determine states of a current running through wirings of the integrated circuit device 100. Thus, a failure analysis is made by comparing the thus determined current states with design data, or with an equivalent circuit which normally operates.
In the conventional failure analysis equipment illustrated in FIG. 1, the in-circuit tester 22 measures voltages of many sections of the target electronic circuit 100 for identifying failure sites and the causes of the failure. However, if the target electronic circuit 100 mounts elements thereon in high density, it is often difficult, in some cases maybe impossible, to measure a voltage of a target point due to such elements mounted with high density. In addition, since wirings mounted on a substrate are covered with a protection film, it is necessary to remove such a protection film in order to measure a voltage of the sections of the target electronic circuit 100. Thus, the conventional failure analysis equipment has a problem that it is impossible to identify failure sites and the causes of failure without direct contact to and damage to the target electronic circuit.
Similarly to the above mentioned conventional failure analysis equipment, the failure analysis equipment illustrated in FIG. 2 has to render the probes 23 in physical contact with the target circuit 100. Hence, with higher integration of an integrated circuit, it is more difficult to put the probes 23 at a desired point in the target circuit 100. In addition, there is a fear that the probes 23 themselves work as a load against the target circuit 100, and may exert a harmful influence on the operation of the target circuit 100. Furthermore, the target circuit 100 may be damaged by putting the probes 23 on the target circuit 100.
A typical failure analysis technique is reported in a paper "A METHOD OF DETECTING HOT SPOTS ON SEMICONDUCTORS USING LIQUID CRYSTALS" by John Hiatt in CH 1619-6/81/0000-0130, pp 130-133, 1981, IEEE/PROC. IRPS. This paper reports a failure analysis technique using cholesteric liquid crystals and polarized light to locate areas of high power dissipation on an integrated circuit. According to this paper, the technique is non-destructive and can be performed in a few minutes using common failure analysis equipment. An example is given involving the analysis of a CMOS latch-up mechanism.